Florent VAUTRIN 102 connecties

Electricity and semiconductors field.

The main tasks of an examiner are to search and examine patent applications received by the EPO. Patent applications are texts and drawings describing an invention and submitted by individuals or companies seeking legal protection.

* The purpose of the search is to find the most relevant previously published technical disclosures ("prior art") against which the patentability of the application can be assessed.
* Substantive examination enables the applicant (or authorised representative such as a patent attorney) to be informed of any objections to the grant of a patent, with a view to resolving these through correspondence and, where necessary, oral proceedings.
* Examiners may also be involved in opposition proceedings if the patent is contested.

* High level methodology : development and support of a flow (with an exhaustive QA) to put in production OPC recipes.
* Responsible for the optimization and support of model-based OPC solutions from 120nm to 45nm process technologies.
* UNIX support within the team (C-shell, Tcl/Tk)
* Development and calibration of lithography technology files for DFM/litho aware tools. Work with external suppliers.

Manage memory cells (SRAM, ROM..) reference libraries in submicron technologies (from 120nm to 45nm) within the Crolles2 Alliance
* Development of a CAD flow (with QA check) to deliver products to designers, support and training given to co-workers and CAD teams.
* Design of instances used to build a memory array: a common methodology has been put in place within the Alliance. Support and training given to designers.
* Development of memory cell characterization flow based on ELDO to validate the spice models (used by spice development team). Support to users.

* Read amplifier study : statistical analysis by simulations with ELDO
* Design and optimization of eDRAM memory array
* Design of eDRAM blocks for testchips in 120nm and 90nm technologies